VPN-Problem: DNS-Reihenfolge in /etc/resolv.conf passt nicht, daher eine Priorisierung der VPN-DNS
Workaround: Reihenfolge ändern:
/etc/resolvconf/update.d/libc
### Make the file ###
: > "$TMPFILE"
[ -f "$HEADFILE" ] && cat "$HEADFILE" >> "$TMPFILE"
NAMESRVSTR=""
for N in $NMSRVRS ; do NAMESRVSTR="nameserver $N\n${NAMESRVSTR}" ; done
echo $NAMESRVSTR >> "$TMPFILE"
[ "$SRCHS" ] && echo "search $SRCHS" >> "$TMPFILE"
[ "$RSLVCNFFILES" ] && sed -e '/^[[:space:]]*$/d' -e '/^[[:space:]]*#/d' -e '/^[[:space:]]*\(\(nameserver\)\|\(search\)\|\(domain\)\)[[:space:]]/d' $RSLVCNFFILES >> "$TMPFILE" 2>/dev/null
[ -f "$TAILFILE" ] && cat "$TAILFILE" >> "$TMPFILE"
Berni
Friday, October 21, 2011
Thursday, September 29, 2011
Linux: EDK, Modelsim PATH in bash.bashrc
Add these lines at the end of /etc/bash.bashrc
#xilinx impact
export XIL_IMPACT_USE_LIBUSB=1
#modelsim
export PATH=/opt/modelsim/modeltech/bin:${PATH}
export LM_LICENSE_FILE=/opt/modelsim/lic.dat
export MGLS_LICENSE_FILE=${LM_LICENSE_FILE}
#androit path
export PATH=/opt/android-sdk-linux_x86/tools:${PATH}
#export JAVA_HOME=/usr/lib/jvm/java-6-sun/jre
#xilinx impact
export XIL_IMPACT_USE_LIBUSB=1
#modelsim
export PATH=/opt/modelsim/modeltech/bin:${PATH}
export LM_LICENSE_FILE=/opt/modelsim/lic.dat
export MGLS_LICENSE_FILE=${LM_LICENSE_FILE}
#androit path
export PATH=/opt/android-sdk-linux_x86/tools:${PATH}
#export JAVA_HOME=/usr/lib/jvm/java-6-sun/jre
Thursday, May 26, 2011
Friday, May 13, 2011
Matlab: Symbolic Calculating
http://www.mathworks.com/help/toolbox/symbolic/f3-157665.html#f3-155157
Define variables:
syms x a
Define function:
f = x^2
Solve expression:
solve('x^2 + 1')
Define variables:
syms x a
Define function:
f = x^2
Solve expression:
solve('x^2 + 1')
Simplify expression:
simplify(x^2 + 1 + x^2)
Monday, May 9, 2011
Linux/Shell: copy recursive by file extention
cp `find ./srcfolder -name \*.m` ./dstfolder/
*.m is the file extention
*.m is the file extention
Wednesday, April 6, 2011
C++: Unsigned int to Bin-Output
void print_bin(unsigned int num) {
for(int i=31; i>=0; i--) {
if(num & (1<<i)) {
cout << "1";
} else {
cout << "0";
}
}
cout << endl;
}
Tuesday, January 4, 2011
VHDL: Change Endianess
This two VHDL functions change the endianess. This enables to change from Big to Little Endian and vice versa. It is assumed that 1 byte are 8 bits.
-- changes the endianess BIG <-> LITTLE
function ChangeEndian(vec : std_ulogic_vector) return std_ulogic_vector is
variable vRet : std_ulogic_vector(vec'range);
constant cNumBytes : natural := vec'length / 8;
begin
for i in 0 to cNumBytes-1 loop
for j in 7 downto 0 loop
vRet(8*i + j) := vec(8*(cNumBytes-1-i) + j);
end loop; -- j
end loop; -- i
return vRet;
end function ChangeEndian;
function ChangeEndian(vec : std_logic_vector) return std_logic_vector is
begin
return std_logic_vector(ChangeEndian(std_ulogic_vector(vec)));
end function ChangeEndian;
-- changes the endianess BIG <-> LITTLE
function ChangeEndian(vec : std_ulogic_vector) return std_ulogic_vector is
variable vRet : std_ulogic_vector(vec'range);
constant cNumBytes : natural := vec'length / 8;
begin
for i in 0 to cNumBytes-1 loop
for j in 7 downto 0 loop
vRet(8*i + j) := vec(8*(cNumBytes-1-i) + j);
end loop; -- j
end loop; -- i
return vRet;
end function ChangeEndian;
function ChangeEndian(vec : std_logic_vector) return std_logic_vector is
begin
return std_logic_vector(ChangeEndian(std_ulogic_vector(vec)));
end function ChangeEndian;
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